The present invention generally relates to semiconductor integrated circuit structures and, more particularly, to electrical interconnection structures formed of copper in integrated circuit devices.
Well-recognized improvements in performance, functionality and economy of manufacture have led to integrated circuit designs at extreme levels of device density and reduced size of electronic structures, such as transistors and capacitors, and conductive interconnections between them. At the same time, higher clock rates have increased requirements for low resistance of interconnection structures and reduced capacitive coupling between them in order to reduce signal propagation time while subjecting such structures to increased thermal cycling, often of increased severity. Moreover, increased integration density places more stringent requirements for reliability of interconnections on structures of increased complexity with increased numbers of regions which may be relatively more subject to failure, possibly causing failure of an entire device.
In the past few years, copper has been substituted for aluminum in selected structures or layers or even throughout high performance integrated circuits to achieve reduced connection resistance, good mechanical strength and more rapid signal propagation even though copper has relatively poor adhesive strength to other materials and vice-versa unless complex and special processing is employed and which may result in compromise of electrical properties. In some cases, recently developed insulating materials having a low dielectric constant (e.g. below 4.0), referred to as low-k materials, have also been used.
However, the low bulk resistance of copper, as well as its mechanical strength, can be compromised by contamination or additional materials provided, for example, to increase adhesion between layers and/or reduce electromigration of conductor material. Low-k materials can also be subject to contamination, particularly in regard to materials that may cause corrosion of copper and may also cause mismatches of thermal expansion coefficients that can impose increased mechanical stresses on copper conductors and thus may drive breakage of weak vias. As the via-line contact from one interconnect level to another involves several intermediate processing steps between the respective metallizations, including breaking the vacuum, depositing a cap and interlayer dielectric, etching, stripping, cleaning and the like, there is significant opportunity for contamination and/or oxidation of this interface.
As such, the predominant yield and defect reliability defect failure mechanism in all types of multi-level on-chip metallization schemes tends to be at this via-line interface. That is, the layered nature of integrated circuit devices tends to increase the possibility of contamination of surfaces and/or alloying of materials with unpredictable results which may be contrary to the result intended or which may, for example, improve electro-migration or adhesion properties while degrading bulk resistance or vice-versa. Properties of alloys can also change radically with relative concentration of alloying materials and unreacted materials may diffuse and cause such changes in concentration during thermal cycling.
For example, alloying tin, indium and/or magnesium and the like with copper to reduce electro-migration without adversely affecting bulk resistance has been attempted. However, it has been found that such alloying materials getter contaminants such as sulfur and oxygen which increase bulk resistance by alloy scattering and may impede copper grain growth after electroplating, for further resistance increase. In other cases, differing solubility of alloying materials in copper or copper in other materials has required complex processing to regulate alteration of alloy composition or other undesirable effects such as copper precipitation.
In summary, while copper interconnections and via structures can potentially provide greatly improved performance by reducing signal propagation time, that performance enhancement may be compromised and the likelihood of a number of failure modes is increased due to the strong tendency toward compromised adhesion to copper as well as difficulty of avoiding or regulating reaction of copper with other materials which may cause increase of bulk resistance or adhesive weakness or both. Such weakness, tending to cause breakage, or increased bulk resistance is generally encountered at the interface of interconnection and via structures where different materials may be layered and/or contamination is most likely and where it is most difficult to avoid reaction of copper without substantial increase of processing complexity. This problem is common, albeit to differing degrees, to all multi-level metallization schemes such as aluminum, silver, gold and tungsten.